1. Field of the Invention
The present invention relates to a logic simulator for performing logic simulation of a semiconductor device.
2. Description of the Related Art
A semiconductor device generally includes a logic circuit constructed by a large number of logic elements. For example, when a new semiconductor device is to be designed, logic elements are logic-simulated by a logic simulator to check whether a designed logic circuit operates as expected. Such a logic simulator is conventionally arranged by software by using a versatile computer or the like.
In order to increase an operation speed in logic simulation performed by a logic simulator, Published Unexamined Japanese Patent Application Nos. 59-3652 or 63-257841 propose a logic simulator in which a portion of software of the logic simulator as described above is replaced by hardware.
In recent years, however, as a packing density of a semiconductor device has been increased, a simulation logic to be simulated by a logic simulator has been large-scale-integrated and complicated. In a conventional logic simulator in which a portion of software is replaced by hardware, therefore, simulation sometimes take several to several tens of hours.